HalpTscReserveResources

CHAR __fastcall HalpTscReserveResources(INT64 a1){
  unsigned int MaximumRegisteredProcessorCount; 
  __int64 v2; 
  __int64 v3; 
  ULONG_PTR v4; 
  __int64 v5; 
  __int64 v6; 
  HalpTscFallbackLock = 0i64;
  MaximumRegisteredProcessorCount = HalpQueryMaximumRegisteredProcessorCount(a1);
  v2 = MaximumRegisteredProcessorCount;
  if( *(_DWORD *)(HalpPerformanceCounter + 228) == 5 )
  {
    v3 = (4 * MaximumRegisteredProcessorCount
        + ((4 * MaximumRegisteredProcessorCount + 8 * MaximumRegisteredProcessorCount + 7) & 0xFFFFFFF8)
        + 7) & 0xFFFFFFF8;
    v4 = ((((_DWORD)v3 + 4 * MaximumRegisteredProcessorCount + 7) & 0xFFFFFFF8)
        + (MaximumRegisteredProcessorCount << 7)
        + 135) & 0xFFFFFFF8;
    v5 = HalpMmAllocCtxAlloc(v3, v4);
    v6 = v5;
    if( !v5 )
      KeBugCheckEx(0xACu, v4, 0xAB00ui64, (ULONG_PTR)"minkernel\\hals\\lib\\timers\\pc\\tscsync.c", 0x15Eui64);
    memset(v5, 0i64);
    HalpTscDeltas = v6;
    HalpTscMaximumCounterSyncSpread = 1024;
    HalpTscNopCycles = (v6 + 8 * v2 + 7) & 0xFFFFFFFFFFFFFFF8ui64;
    HalpTscWaves = (HalpTscNopCycles + 4 * v2 + 7) & 0xFFFFFFFFFFFFFFF8ui64;
    HalpTscSkewOffset = (HalpTscWaves + 4 * v2 + 7) & 0xFFFFFFFFFFFFFFF8ui64;
    TscRequest = (((HalpTscSkewOffset + 4 * v2 + 7) & 0xFFFFFFFFFFFFFFF8ui64) + 120) & 0xFFFFFFFFFFFFFF80ui64;
    LOBYTE(MaximumRegisteredProcessorCount) = HalpTscCheckAdjustMsrCapability();
    HalpTscAdjustAvailable = MaximumRegisteredProcessorCount;
  }
  return MaximumRegisteredProcessorCount;
}

Referenced by: